Applications requiring the division of a signal of predetermined frequency by various divisors are quite common. The general class of frequency divider circuits typically receives, as an input signal, a reference clock signal with a fixed frequency. Previous frequency divider circuits have divided the clock signal by both integer, and less commonly, non-integer divisors. As is readily apparent, frequency divider circuits have broad utility in digital circuits which utilize a plurality of multiples of a predetermined signal. Specific applications include video or television displays, video encoders, home computers, Integrated Services Digital Network (ISDN) integrated circuits, and the like.
In a known frequency divider, as described by Jacob Luscher in U.S. Pat. No. 4,295,056 entitled "Integrated Frequency Divider", a shift register, comprising a plurality of cells serially connected one after the other, is supplied with two periodic signals. Circuitry is utilized for detecting a particular state of the shift register. A signal generator, responsive to the detecting of the state, is also provided for producing a signal with a frequency which is a sub-multiple of the periodic signals. This known frequency divider is especially well adapted to applications requiring the division of high frequency signals with minimal power consumption, as in quartz oscillator watches, but is limited to division by integer value divisors.
In another known frequency divider, as described in U.S. Pat. No. 4,193,037, entitled "Frequency Divider Circuit With Selectable Integor/ Non-Integer Divison" by Kyuetal, an input signal of a predetermined frequency is selectively divided by both integer and non-integer values. Logic circuitry responsive to predetermined transitions in first and second clock signals is provided for generating a series of output signals having frequencies which are predetermined integer and non-integer multiples of the clock signals. The output signals are respectively delayed delayed with respect to each other. The output signals are logically combined in order to generate both integer or non-integer multiples of the clock signals. This type of known frequency divider provides an inexpensive frequency divider circuit which can select either integer or non-integer divisors depending upon a control signal, but which may be susceptible to clock skew. Previous frequency dividers often utilize circuitry which requires a distributed network of clock signals for synchronization. Skew in the clock signals, with respect to each other, may reduce accuracy in the frequency of the generated signal. Additionally, other frequency dividers may require significantly additional logic circuitry in order to generate a given integer or non-integer multiple of two clock signals. Consequently, propagation delays or latency in known frequency dividers may be a function of a given integer or non-integer divisor.